| Xelerated and Teradiant Demonstrate Interoperability at 40Gbps | |||
| Posted by: Jordi on Wednesday, October 22, 2003 - 06:17 PM | |||
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Xelerated, developer of the first single-chip, 40Gbps network processor, and Teradiant, developer of the first single-chip, 40Gbps traffic manager, today announced availability of a joint solution targeting high-performance, high functionality, cost optimized metro Ethernet systems. | ||
| Targeting a range of advanced applications such as VPLS, MPLS, Martini Draft, IPv6, IPv4, and Diffserv for metro core, metro edge and metro access, the solution demonstrates the ability to provide deterministic 40Gbps performance and advanced queuing for all packet sizes. For example, the network processor, traffic manager switch and associated memory devices consume only 14.6W per 10Gbps in 40Gbps configurations. The chips' high levels of integration enable system vendors to achieve full-duplex bandwidth at less than $500 per 10Gbps for these components. Click here for the complete info. |
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